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5aefb29a95
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Experiment with VM optimization
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2025-02-11 09:28:02 -05:00 |
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59f64c9afd
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Fix register closing
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2025-02-11 05:29:00 -05:00 |
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f2ee01d66f
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Add comparison tests for less than operator; Implement less than operator in VM
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2025-02-11 02:22:14 -05:00 |
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3af1b64820
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Reimplement more instruction and compiler logic
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2025-02-08 17:36:30 -05:00 |
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07001a03e7
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Add tests for divide instruction
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2025-02-08 11:58:30 -05:00 |
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6e9d5a49d2
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Add tests for multiply instruction
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2025-02-08 11:45:03 -05:00 |
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1bb87de70f
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Add tests for subtract instruction
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2025-02-08 11:35:58 -05:00 |
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71a92c078b
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Add formatting disassembly output into JSON or TOML
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2025-02-08 05:56:49 -05:00 |
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e387579a81
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Extend and pass tests
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2025-02-08 00:17:15 -05:00 |
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d3addbe183
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Fix and pass all tests
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2025-02-07 22:39:07 -05:00 |
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ac11ad5674
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Refactor instruction layout to allow for more type codes
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2025-02-07 20:52:08 -05:00 |
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1d0824165d
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Implement lists; Add tests
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2025-02-07 17:40:08 -05:00 |
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8cc5661944
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Begin rewriting tests
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2025-02-07 15:37:48 -05:00 |
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72421bf510
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Fix compiling of comparison expressions; Implement LoadEncoded in the VM
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2025-02-07 13:29:14 -05:00 |
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25b4230aa4
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Use Operand type to store instruction argument types
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2025-02-07 10:19:38 -05:00 |
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788e3d4a2b
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Clean up
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2025-02-06 17:25:46 -05:00 |
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75d6948e82
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Consolidate point instructions into return instructions
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2025-02-06 14:34:31 -05:00 |
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bd273035aa
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Convert LoadBoolean to LoadEncoded; Fix register handling
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2025-02-06 13:10:11 -05:00 |
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6f0955c29a
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Improve control flow register consolidation
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2025-02-06 12:42:55 -05:00 |
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6d17ba9a2c
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Clean up
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2025-02-05 19:29:15 -05:00 |
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4775d425a0
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Implement typed registers with untyped constants
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2025-02-05 19:12:26 -05:00 |
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12092c30f4
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Roll back slightly
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2025-02-03 18:08:03 -05:00 |
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371a061b1c
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Consolidate local operations to point operations
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2025-02-03 17:49:38 -05:00 |
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c1fe54ccd5
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Attempt alternative to total register overhaul
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2025-02-03 15:05:32 -05:00 |
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1409698fdd
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Fix some bugs to get language working with new 64-bit instructions
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2025-01-13 10:37:54 -05:00 |
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ac1ee793ab
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Use fewer operations and encode operand types in the instruction
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2025-01-13 09:49:08 -05:00 |
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0510e18060
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Begin implementing typed 64-bit instructions
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2025-01-13 06:01:38 -05:00 |
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61f4093da0
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Edit README; Begin 64-bit instruction set
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2025-01-10 12:54:33 -05:00 |
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9d370aea2a
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Fix function calling bug
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2025-01-09 02:25:06 -05:00 |
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6cfa0f58e3
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Improve VM layout and performance
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2025-01-08 10:29:53 -05:00 |
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e9bd9b37b0
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Make runtime improvements
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2025-01-08 04:21:01 -05:00 |
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2c0da440ef
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Fix bugs in the VM and compiler
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2025-01-04 02:56:46 -05:00 |
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56becbfacb
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Fix register-setting bug
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2025-01-01 21:53:54 -05:00 |
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d7289414f4
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Fix some aspects of the compiler for logic and semicolons
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2024-12-17 18:11:06 -05:00 |
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72365cd399
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Continue new VM implementation; Write docs
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2024-12-17 16:31:32 -05:00 |
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4527f7b6ef
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Continue thread-based VM refactor
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2024-12-17 07:10:47 -05:00 |
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bd590e0643
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Begin VM conversion to multi-thread
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2024-12-17 03:22:44 -05:00 |
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9ae923febd
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Optimize; Revert to branch-style comparisons for performance
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2024-12-14 00:45:49 -05:00 |
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1777ad298b
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Experiment wih more optimizations
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2024-12-11 09:26:38 -05:00 |
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395f0af213
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Use a lookup table instead of matching operation codes in the VM
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2024-12-11 08:39:48 -05:00 |
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20f451fe6c
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Experiment with optimizations and benches
|
2024-12-11 06:49:43 -05:00 |
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1c32cd0956
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Break up tests; Write docs
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2024-12-11 01:22:40 -05:00 |
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5aa8579fae
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Write docs; Flesh out the benchmarks; Clean up
|
2024-12-10 08:04:47 -05:00 |
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85a706e0fb
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Make the disassembly prettier than ever before
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2024-12-10 01:34:53 -05:00 |
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5d43674000
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Continue refactor and rewrite comparison operator compilation
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2024-12-09 10:30:57 -05:00 |
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98a7b7984a
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Continue refactor; Condense registers in logic chains
|
2024-12-09 08:27:45 -05:00 |
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a9e867aaab
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Continue rewrite of instructions and operations
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2024-12-09 07:01:07 -05:00 |
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cc069df7ee
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Continue instruction rewrite
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2024-12-08 08:01:15 -05:00 |
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1fa958fd0b
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Restart instruction refactor
|
2024-12-08 06:04:01 -05:00 |
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215601707b
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Clean up code and docs
|
2024-12-02 01:08:41 -05:00 |
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