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3af1b64820
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Reimplement more instruction and compiler logic
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2025-02-08 17:36:30 -05:00 |
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6f0955c29a
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Improve control flow register consolidation
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2025-02-06 12:42:55 -05:00 |
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ac1ee793ab
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Use fewer operations and encode operand types in the instruction
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2025-01-13 09:49:08 -05:00 |
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0510e18060
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Begin implementing typed 64-bit instructions
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2025-01-13 06:01:38 -05:00 |
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e9bd9b37b0
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Make runtime improvements
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2025-01-08 04:21:01 -05:00 |
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d7289414f4
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Fix some aspects of the compiler for logic and semicolons
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2024-12-17 18:11:06 -05:00 |
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1777ad298b
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Experiment wih more optimizations
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2024-12-11 09:26:38 -05:00 |
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20f451fe6c
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Experiment with optimizations and benches
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2024-12-11 06:49:43 -05:00 |
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a9e867aaab
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Continue rewrite of instructions and operations
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2024-12-09 07:01:07 -05:00 |
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cc069df7ee
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Continue instruction rewrite
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2024-12-08 08:01:15 -05:00 |
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7e2ebf54c7
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Use new instruction features
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2024-11-28 05:36:10 -05:00 |
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a94cc11069
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Refactor to use 64-bit instructions
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2024-11-26 07:14:30 -05:00 |
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